WORKSHOP PAPER
Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel
Tarek Al Abbas1,2, Danial Chitnis2, Francesco Mattioli Della Rocca2, Robert K. Henderson2
1Sense Photonics, Edinburgh, UK
2School of Engineering, Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh, UK, EH9 3FF

Abstract

A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼70ps at 2V excess bias and 773nm showing no degradation to temporal resolution.
Publisher: IISS (Int. Image Sensors Society)
Year: 2019
Workshop: IISW
URL: https://doi.org/10.60928/0gsc-8nqe
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Keywords

3D-stacked CMOS technology, single photon avalanche diode (SPAD), dynamic range (DR) extension,

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