WORKSHOP PAPER
Cmos Image Sensor Pixel with 2D CCD Memory Bank for Ultra High Speed Imaging with Large Pixel Count
A. Lahav1, J. Crooks2, B. Marsh2, R. Turchetta2, A. Fenigstein1
1TowerJazz Semiconductor Ltd, Migdal Haemek, Israel
2STFC Rutherford Appleton Laboratory, Didcot, Oxfordshire, UK

Abstract

We present the design and optimization of a 30um CMOS Image Sensor (CIS) pixel. This pixel is embedded in a sensor working in burst mode at speeds up to 5Mfps and high resolution (0.7Meg). Such performance is achieved using two dimensional CCD Memory bank at each pixel which was manufactured using a 0.18um well established CIS Process.
Publisher: IISS (Int. Image Sensors Society)
Year: 2013
Workshop: IISW
URL: https://doi.org/10.60928/1mf9-rcdv
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Keywords

CCD in CMOS, Buried Channel, Charge Transfer, Global Shutter, CDS,

References

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