WORKSHOP PAPER
A 400×96 14,467-fps Scan Rate Low Rolling Shutter Distortion CMOS Image Sensor using 12-bit Error- Averaging Column Parallel Pipelined ADC
Abstract
This paper presents a 12-bit high resolution column parallel pipelined ADC architecture achieving 0.5 µs Analog-to-Digital conversion time, DNL of +0.62 / -0.88 DN, and random noise of 245 µVrms obtained in an ADC TEG chip. We also designed and fabricated a 400 (H) × 96 (V) 8.48 µm pixel pitch CMOS image sensor integrating a revised column parallel ADC and achieved 0.36 µs conversion time, resulting in the maximum scan rate of 14,467 fps. This sensor is suitable for Rolling Shutter Distortion-less imaging and video shooting applications such as machine vision application.Keywords
CMOS image sensor, pipelined ADC, analog-to-digital conversion,References
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