WORKSHOP PAPER
In-Pixel Storage Techniques for CMOS Burst-Mode Ultra-High-Speed Imagers
L. Wu1,2, D. San Segundo Bello2, P. Coppejans2, A. Süss2, M. Rosmeulen2, J. Craninckx2, P. Wambacq1,2, J. Borremans2
1Vrije Universiteit Brussel (VUB), Dept. of Electronics and Informatics (ETRO), Brussels, Belgium
2imec, Heverlee, Belgium

Abstract

This work presents in-pixel circuit techniques for burst-mode ultra-high-speed imagers to improve the noise performance while maintaining a dense analog memory storage for each pixel. Together with an AC coupling CDS stage, in-pixel amplification is demonstrated to be useful to improve effective frame depth for longer recording time. Considering the benefits on scaling and power consumption, a 108-cell memory bank (10fF/cell) is implemented inside the pixel. Two types of pixel variations were fabricated in CMOS 130nm technology. The photon transfer curves of both pixel types are measured over different operation speeds up to 20Mfps showing noise performance of both variations to be less than 10e- noise.
Publisher: IISS (Int. Image Sensors Society)
Year: 2017
Workshop: IISW
URL: https://doi.org/10.60928/3z1q-kha2
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Keywords

In-Pixel Storage, Burst-Mode Imagers, Low Noise Performance,

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