WORKSHOP PAPER
New Integration Technology of Small-Pixel CIS with High Sensitivity
Seounghyun Kim1, Taegyu Kim, Munhwan Kim, Dongbin Park, Heesung Shim, Jongtaek Hwang, Sungho Jun, Ohjin Jung, Joonku Yoon, Minhyung Lee, Chulho Park, Jaewon Han, Joon Hwang
1CIS Process Development Team, Mixed Foundry Division, Dongbu HiTek Co., Ltd., 474-1 Sangwoo-Ri, Gamgok-Myeon, Eumseong-Gun, Chungbuk, 369-852, Korea

Abstract

We have developed the new pixel structure using the wafer to wafer bonding and the cleaving technologies, by which we can maximize photodiode area. The new technology consists of 4 steps; Logic wafer integration, Top photodiode integration, wafer bonding and cleaving, process after cleaving. As the results, we obtained a good image quality despite of small pixel as well as reduce the chip size, because the new structure has no metal levels issue. Although we got the good results more than expected, we should optimize top photodiode doping conditions and improve bonding quality.
Publisher: IISS (Int. Image Sensors Society)
Year: 2009
Workshop: IISW
URL: https://doi.org/10.60928/42zj-vte1
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Keywords

CMOS Image Sensor, Pixel Structure, Wafer Bonding,

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