WORKSHOP PAPER
A 1/3.4-inch 2.1-Mpixel 240-frames/s CMOS Image Sensor
Seunghyun Lim1, Jimin Cheon1, Youngcheol Chae1, Wunki Jung2, Dong-Hun Lee2, Seogheon Ham2, Dongsoo Kim1, Gunhee Han1
1Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
2System LSI Division, Semiconductor Business, Samsung Electronics Co., Yongin-City, Kyungki-Do, Korea

Abstract

This paper proposes a 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic ADC that consumes low power of 90 μW/column at 1.5 V supply and is applicable to the fine pixel pitch of 2.25 μm. The prototype sensor was fabricated in a 0.13-μm 1P4M CMOS technology. The measured DNL and INL are +0.59/-0.83 LSB and +2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with a low power of 300 mW.
Publisher: Samsung Electronics Co. Ltd.
Year: 2009
Workshop: IISW
URL: https://doi.org/10.60928/5py6-799g
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Keywords

CMOS image sensor, cyclic ADC, low power consumption,

References

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