WORKSHOP PAPER
A 4K2K 60-fps Image Sensor Based on Stagger-laced Dual-exposure Technique
Yusuke Okada1, Takeo Azuma1, Toshinobu Matsuno1, Hiroyoshi Komobuchi1, Jan Craninckx2, Bertrand Parvais2, Kyriaki Minoglou2, Koen De Munck2, Luc Haspeslagh2, Piet De Moor2, Serge Biesemans2,3
1Panasonic Corporation, 3-4 Hikaridai, Seika-cho, Soraku-gun, Kyoto 619-0237, Japan
2imec, Kapeldreef 75, 3001 Heverlee, Belgium
3TEL Europe,

Abstract

This study describes a 12-bit, 4K2K 60-fps CMOS image sensor capable of reducing the pixel readout rate without degrading resolution of the output images. The data reduction is done by a novel 'stagger-laced' scan, which reduces the data rate by half by alternate readout of two sets of horizontal pixel pairs arranged in two complementary checkerboard patterns. For the 12-bit, 60-fps readout of 4K2K pixels, the column delta-sigma (∆Σ) ADCs are employed. The chip is fabricated using imec 130-nm 1P3M CMOS process. Experimental results show the proposed stagger-laced scanning followed by an image restoration process little degrades the image resolution from the progressive one in spite of the half number of pixels read out, as well as enhances the image SNR.
Publisher: IISS (Int. Image Sensors Society)
Year: 2013
Workshop: IISW
URL: https://doi.org/10.60928/7koc-atvi
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Keywords

4K2K image sensor, stagger-laced scan, delta-sigma ADC,

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