WORKSHOP PAPER
An Extremely High-Speed and Low-Power Digital Pixel Sensor with Advanced Sensor Architecture
Myunglae Chu1, Min-Woong Seo1, Suksan Kim1, Hyun-Yong Jung1, Jiyoun Song1, Sung-Jae Byun1, Minkyung Kim1, Daehee Bae1, Junan Lee1, Sung-Yong Kim1, Jongyeon Lee1, Jonghyun Go1, Jae-kyu Lee1, Changrok Moon1, Hyoung-Sub Kim1
1Samsung Electronics, Hwaseong-si, Republic of Korea

Abstract

This paper presents an extremely high-speed of 1200 fps global-shutter (GS) CMOS image sensor (CIS). A GS CIS is a great alternative to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-dimensional image data can be simultaneously sampled by the in-pixel analog memory. In order to achieve a high speed global-shutter operation, we proposed a novel architecture, using a pixel-wise ADC and an in-pixel digital memory, for the digital pixel sensor (DPS) which is a remarkable global-shutter operation CIS. Within 4.95-μm, one ADC and 22-bit memories are integrated by using two small-pitch Cu-to-Cu interconnectors for the wafer-level stacking. The 2-mega pixels (Mp) array, 1668H×1364V, prototype image sensor is successfully fabricated and demonstrated.
Publisher: IISS (Int. Image Sensors Society)
Year: 2021
Workshop: IISW
URL: https://doi.org/10.60928/9wao-wmu8
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Keywords

High-Speed CMOS Image Sensor, Global-Shutter, Digital Pixel Sensor,

References

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