WORKSHOP PAPER
1.0um pixel improvements with hybrid bond stacking technology
V.C. Venezia1, C. Shih1, W.Z. Yang1, Y. Zang1, Z. Lin1, L. A. Grant1, H. Rhodes1
1Omnivision Technologies, Santa Clara CA 95054

Abstract

In this work, Omnivision’s second-generation (Gen2), 1.0um CMOS image-sensor technology is presented. The key features of this Gen2 technology are hybrid-bond (HB) stacking, backside deep trench isolation (BS-DTI), a new backside composite metal-oxide grid (CMG), and improved gate oxide quality. The Gen2, 1.0-um pixel products achieve 20% higher full well capacitance, 12.5% higher sensitivity, 10-lux lower SNR10, 2x lower RTS noise, and a 10% reduction in chip size. Results are demonstrated on 16- and 20-MP array products.
Publisher: IISS (Int. Image Sensors Society)
Year: 2017
Workshop: IISW
URL: https://doi.org/10.60928/aocx-788h
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Keywords

CMOS image-sensor technology, hybrid-bond stacking, backside deep trench isolation,

References

1) V.C. Venezia et al, "Stack Chip Technology: A New Direction for CMOS Imagers", Proc. IISW, 2015. https://doi.org/10.60928/l6of-zcb8
2) Chi Han_Lin et al, "1.1um Back-Side Illuminated Image Sensor Performance Improvement", Proc. IISW, 2013. https://doi.org/10.60928/h71e-9nz2