WORKSHOP PAPER
Fully Depleted CIS Pixel Using Reverse Substrate Bias without Undesirable Leakage Currents
Swaraj Bandhu Mahato1,2, Jean-Luc Bacq1, Pierre Boulenc1, Yun-Tzu Chang1, Bert van Lijnschoten1, Antonia Malainou1, Celso Cavaco1
1imec, Kapeldreef 75, B-3001 Leuven, Belgium
2Gpixel NV, Antwerp, Belgium

Abstract

Earlier, IMEC has demonstrated a fully depleted CIS pixel device with a sufficiently large reverse substrate bias or back bias. In this paper, we report an updated device structure that circumvents the die leakage and punch-through in the peripheral circuit area and is used in an ultra-high speed CMOS image sensor. The updated device structure is designed and studied through TCAD simulations and validated through leakage measurement and pixel characterization.
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/ckt7-1jio
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Keywords

fully depleted, CIS pixel, reverse substrate bias, leakage currents, ultra-high speed, CMOS image sensor,

References

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