WORKSHOP PAPER
A Study on a Feature Extractable CMOS Image Sensor for On-Chip Image Classification
Shunsuke OKURA1, Yudai MORIKAKU1, Yu Osuka1, Ryuichi UJIIE, Daisuke MORIKAWA2, Hideki SHIMA2, Kota YOSHIDA1
1Ritsumeikan University, 1-1-1 Noji-higashi, Kusatsu, Shiga, 525-8577 JAPAN
2Nisshinbo Micro Devices Inc.,

Abstract

In the emerging IoT era, a CMOS image sensor (CIS) that can output features required for AI recognition is expected to reduce the power consumption of image recognition systems. In this paper, we propose an on-chip signal processing pipeline to extract two channels of feature data composed of 1-bit grayscale intensity and horizontal edges for a 2.0T pixel CMOS image sensor. Additionally, a tiny neural network model for on-chip AI processing is verified to examine image classification accuracy. According to simulation results, the image classification accuracy with the feature data reached 79.8%, even though the effective data volume of the feature data is reduced to only 0.7% of that of the 8-bit RGB color image. The memory occupation flow for a 2 Mpixel 60 fps CIS is also estimated to consider the feasibility of implementing an on-chip image classifier. Around 60 kB of peak memory and weight memory are additionally required for the processing, which is only 17 times the line memory required to serialize the RGB color image.
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/ddyo-gwws

Keywords

Image classification, Artificial neural networks, CMOS image sensors, Feature extraction,

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