WORKSHOP PAPER
Reset noise reduction architectures for the detection of charged particles
R. Turchetta1, T. Anaxagoras1,2, J. Crooks1, A. Godbeer1, T. Pickering1, N. Allinson2, A. Blue3, D. Maneuski3, V. O’Shea3
1Rutherford Appleton Laboratory, Science and Technology Facilities Council (STFC), Harwell Science and Innovation Campus, Didcot, OX11 0QX, U.K
2Sheffield University, Department of Electronic and Electrical Engineering, Sheffield, UK
3University of Glasgow, Department of Physics and Astronomy, Glasgow, UK

Abstract

This paper presents a parametric test sensors designed in a 0.18 μm advanced CMOS Image Sensor process. The sensor includes a number of subarrays with different pixel architectures optimised for low noise. These architectures exploit design techniques to achieve noise lower than the reset noise floor and they are suitable for a straightforward implementation in a radiation resistant sensor, as required in many scientific applications. The sensor was fabricated on a P-type epitaxial substrate, in both 5 and 12 μm thickness. Noise as low as 6 e- rms was demonstrated.
Publisher: IISS (Int. Image Sensors Society)
Year: 2009
Workshop: IISW
URL: https://doi.org/10.60928/ekc4-63fg
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Keywords

reset noise, CMOS image sensors, charged particle detection,

References