WORKSHOP PAPER
In-Fab Parameter Characterization for Pinned Photodiodes in CMOS Image Sensors
Dongseok Cho1,21,2,3, Jae-Kyu Lee22, Jonghyun Go22, Myung-Jae Lee11, Youngcheol Chae1,31,3
1Yonsei University, Seoul, Korea,
2Semiconductor R&D Center, Samsung Electronics, Hwasung, Korea,
3XO Semiconductor Inc., Seoul, Korea,

Abstract

This paper proposes a test methodology that enables early characterization of pinned photodiode (PPD) properties during the CIS fabrication process. The proposed method measures the capacitance of the PPDs simply yet with high precision and facilitates the extraction of key parameters of the PPD. The effectiveness of the proposed method is validated by observing significant changes in these parameters in response to variations in process conditions and the bias voltage of the transfer gate (TG). In addition, the full well capacity (FWC) is successfully extracted from the measured PPD capacitance, consistent with electrical die sorting (EDS) results.
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/f08i-avvm
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Keywords

CMOS, Image Sensors, Pinned Photodiodes, Characterization, Fabrication Process, Capacitance,

References

[1]) D. Kim et al., "A 1/1.56-inch 50Mpixel CMOS image sensor with 0.5 âµm pitch quad photodiode separated by front deep trench isolation", in 2024 IEEE International Solid-State Circuits Conference (ISSCC), IEEE, 2024, pp. 118–120.. https://doi.org/10.1109/isscc49657.2024.10454448
[2]) S. Park and H. Uh, "The effect of size on photodiode pinch-off voltage for small pixel cmos image sensors", Microelectronics Journal, vol. 40, no. 1, pp. 137–140, 2009.. https://doi.org/10.1016/j.mejo.2008.06.071
[3]) V. Goiffon et al., "On the pixel level estimation of pinning voltage pinned photodiode capacitance and transfer gate channel potential", in Proc. Int. Image Sensor Workshop, 2013.