WORKSHOP PAPER
Wafer-Level Thinned Monolithic CMOS Imagers in a Bulk-CMOS Technology
Bedabrata Pain1, Chao Sun1, Paula Vo1, Bruce Hancock1, Thomas J. Cunningham1, Chris Wrigley1, Risaku Toda1, Victor White1, Amrita Banerjee2, Durgmadhab Misra2
1Jet Propulsion Laboratory, California Institute of Technology, 4800 Oak Grove Drive, Pasadena, CA 91109
2Dept of Electrical & Computer Engineering, New Jersey Institute of Technology, 161 Warren St, Newark, NJ 07102

Abstract

This paper focuses on the design, fabrication, and test results of a monolithic 1024x1024 back-illuminated digital CMOS imager and diode test structures fabricated on SOI silicon wafers. It highlights the challenges of monolithic back-illuminated image sensor fabrication such as accurate and uniform wafer-level thinning, surface passivation following thinning, wafer support during thinning, pad opening and packaging.
Publisher: IISS (Int. Image Sensors Society)
Year: 2007
Workshop: IISW
URL: https://doi.org/10.60928/gap3-ejsd
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Keywords

CMOS image sensors, back-illuminated image sensors, wafer-level thinning,

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