WORKSHOP PAPER
A Partial-Multi-Conversion Single-Slope ADC with Response-Linearized RDAC
Akira Matsuzawa1, Abdel Martinez Alonso1, Lilan Yu1, Minhyuk Sung1, Masaya Miyahara1
1Tech Idea Co., Ltd., 1-21-5-1, Shukugawara, Tamaku, Kawasaki, 214-0021, Japan.

Abstract

This paper proposes a Single-Slope column ADC (SSADC) for CMOS Image Sensors (CIS). The response-linearized DAC using digital step pulse injection can realize a fast and accurate ramp wave without increase of power dissipation (Pd). Low Pd of 0.9 μW for a comparator is achieved with a resistive DAC (RDAC). The multi-conversion method is applied only for weak signal of less than 30 mV without significant increase in the conversion time, Tc. As a result, a 12bit SSADC attains a low noise of 32.5 μV and a low Pd of 34 μW while using 8 conversions at the Tc of 4 μs. A high dynamic range of 90 dB and a high Schreier FoM S (DR) of 183 dB are attained with small size of 3.2 μm x 556 μm in 65 nm CMOS.
Publisher: IISS (Int. Image Sensors Society)
Year: 2021
Workshop: IISW
URL: https://doi.org/10.60928/gsjx-odmm
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Keywords

ADC, DAC, LOW NOISE, LOW POWER, CMOS, SENSOR, IMAGE SENSOR, COLUMN ADC, FOM,

References

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