WORKSHOP PAPER
A new 0.8 µm CMOS image sensor with low RTS noise and high full well capacity
Takuma Hasegawa1, Kazufumi Watanabe2, Y. Jay Jung2, Nagataka Tanaka1, Takashi Nakashikiryo1, Wu-Zang Yang3, Alan Chih-Wei Hsiung2, Zhiqiang Lin2, Sohei Manabe2, Vincent C. Venezia2, Lindsay A. Grant2
1OmniVision Technologies Japan, Kanagawa, Japan
2OmniVision Technologies, Santa Clara, CA 95054, USA
3OmniVision Technologies Taiwan, Hsinchu, Taiwan

Abstract

This is a report of a new 0.8µm, 32 mega pixel CMOS image sensor (CIS) with OmniVision second-generation (Gen2) stacking technology. In this work, a pixel layout was redesigned and a vertical transfer gate (VTG) was developed to achieve low noise and high full well capacity (FWC). The sensor achieved a total read noise of 1.2e-rms and a linear FWC of 5000e-. The random telegraph signal (RTS) noise was reduced 70% compared with that of a 0.9µm pixel. Other pixel performance improvements are also realized in this work.
Publisher: IISS (Int. Image Sensors Society)
Year: 2019
Workshop: IISW
URL: https://doi.org/10.60928/hsaw-fzn0

Keywords

CMOS image sensor, low RTS noise, high full well capacity,

References

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