WORKSHOP PAPER
Preliminary Experiment for Precise and Dynamic Digital Calibration for Two-Stage Cyclic ADC Suitable for 33-Mpixel 120-fps 8K Super Hi-Vision CMOS Image Sensor
Toshihisa Watabe1, Kazuya Kitamura2, Tomohiko Kosugi3,4, Hiroshi Ohtake2, Hiroshi Shimamoto2, Shoji Kawahito4
1NHK Engineering System, Inc., 1-10-11 Kinuta, Setagaya-ku, Tokyo, 157-8540, Japan
2NHK Science & Technology Research Laboratories, Tokyo, Japan
3Brookman Technology, Inc., Hamamatsu, Japan
4Research Institute of Electronics, Shizuoka University, Hamamatsu, Japan

Abstract

An ADC operation and signal processing scheme in the error measurement mode has been developed to determine error coefficients. A preliminary experiment was performed by using an ADC test circuit to verify the scheme’s effectiveness for precise and dynamic digital calibration. The calibration process was performed by using the evaluated values of error coefficients in the proposed way, and the results demonstrated that the nonlinearity of the ADC was successfully improved by compensating for errors caused in the ADC due to capacitor mismatch, finite gain and incomplete settling of the amplifier, and offset.
Publisher: IISS (Int. Image Sensors Society)
Year: 2015
Workshop: IISW
URL: https://doi.org/10.60928/ka8l-e3yg
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Keywords

Digital calibration, Cyclic ADC, Super Hi-Vision, 33-Mpixel, 120-fps, CMOS image sensor,

References

1) H. -S. Lee, "A 12-b 600ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC", IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 509-515, 1994. https://doi.org/10.1109/4.280701
2) S. Kawahito, J. –H. Park, K. Isobe, S. Shafie, T. Iida, and T. Mizota, "A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits", Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.56-57, Feb. 2008. https://doi.org/10.1109/isscc.2008.4523054
3) T. Watabe, K. Kitamura, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, K. Isobe, T. Watanabe, H. Shimamoto, H. Ohtake, S. Aoyama, S. Kawahito, and N. Egami, "A 33Mpixel 120fps CMOS Image Sensor Using 12b Column-Parallel Pipelined Cyclic ADCs", Int. Solid-State Circuits Conf. Dig. Tech. Papers, 55, 22.5, pp. 388-389, Feb. 2012. https://doi.org/10.1109/isscc.2012.6177047
4) K. Kitamura, T. Watabe, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, K. Isobe, T. Watanabe, H. Shimamoto, H. Ohtake, S. Aoyama, S. Kawahito, and N. Egami, "A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters", IEEE Trans. Electron Devices vol. 59, no. 12, pp. 3426-3433, 2012. https://doi.org/10.1109/ted.2012.2220364
5) T. Watabe, K. Kitamura, T. Hayashida, T. Kosugi, H. Ohtake, H. Shimamoto, S. Kawahito, and N. Egami, "Digital Calibration Algorithm for a 2-Stage ADC used in 33-Mpixel 120-fps CMOS Image Sensor", Proc. 2013 International Image Sensor Workshop, pp. 277-280, June, 2013. https://doi.org/10.1109/icsens.2014.6984934
6) T. Watabe, K. Kitamura, T. Hayashida, T. Kosugi, H. Ohtake, H. Shimamoto, and S. Kawahito, "Digital Calibration for a 2-Stage Cyclic Analog-to-Digital Converter Used in a 33-Mpixel 120-fps SHV CMOS Image Sensor", ITE Trans. Media Technology and Applications, vol. 2, no. 2, pp. 102-107, 2014. https://doi.org/10.3169/mta.2.102
7) T. Watabe, K. Kitamura, T. Hayashida, T. Kosugi, H. Ohtake, H. Shimamoto, and S. Kawahito, "A Digitally-Calibrated 2-Stage Cyclic ADC for a 33-Mpixel 120-fps Super High-Vision CMOS Image Sensor", Proc. IEEE SENSORS, pp. 66-69, 2014. https://doi.org/10.1109/icsens.2014.6984934
8) J. -H. Park, S. Aoyama, T. Watanabe, K. Isobe, and S. Kawahito, "A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs", IEEE Trans. Electron Devices, 56, 11, pp. 2414-2422, 2009. https://doi.org/10.1109/ted.2009.2030635