WORKSHOP PAPER
Design Mitigations on Pixel and Column ADC for 1 MGy TID and SEE Tolerant CIS
I. Hafizh1, P. Santos1, P. Leroux1, G. Meynants1, J. Van Rethy2, Y. Cao2
1KU Leuven, ADVISE research group, Geel, Belgium
2Magics Technologies, Geel, Belgium

Abstract

This article proposes a new pixel and column ADC with radiation-hardened-by-design mitigations for a CMOS image sensor (CIS) to withstand 1 MGy total ionizing dose (TID) and various single event effects (SEE). The pixel consists of a partially pinned photodiode structure combined with butterfly and dog-bone pixel transistors. The column ADC employs dual sample and hold stages, dual comparators, and dual 10-bit ripple counters, and utilizes only a single-slope conversion cycle. Preliminary results show limited degradation of dynamic range after TID above 1MGy and high temperature annealing (HTA)
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/krbl-nm5o
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Keywords

CMOS image sensor, radiation tolerant, TID, SEE, RHBD, pixel, 3T, column ADC, ripple counter,

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