Abstract

In recent times, there has been explosive growth in use of cameras for hand-held devices as well as automotive applications, which is driving the demand for high-end CMOS image sensors (CIS). Furthermore, it is critical to improve the performance of image sensors as new applications continue to evolve. One of the key approaches to improve CIS performance and device density is pixel scaling, however, this poses some major challenges, e.g. narrowing the CD, increasing the depth of pixels and increasing the pitch can result in increased cross talk and higher dark current. Typically, deep trench isolation (DTI) scheme is utilized for passivation of the trench sidewalls to minimize dark current as well as cross talk. PLAD process (VIISTaTM HVMS) has been successfully integrated for front side DTI (FS DTI) scheme and enables significant gain in key CIS device parametrics by effectively passivating the interface along the trench sidewall.[3] In this work we have evaluated PLAD technique for a back side DTI (BS DTI) scheme for the first time. Initial results demonstrate that PLAD technique can provide effective passivation for BS DTI flow, eventhough the overall thermal budget is low. Additionally, we will also discuss some of the recent developments in sidewall doping characterization techniques and the key mechanisms to further optimize conformality for high aspect ratio (HAR) trench doping.