WORKSHOP PAPER
Evolution of a 4.6 μm, 512×512, ultra -low power stacked digital pixel sensor for performance and power efficiency improvement
Rimon Ikeno1, Kazuya Mori1, Masayuki Uno1, Ken Miyauchi1, Toshiyuki Isozaki1, Hirofumi Abe1, Masato Nagamatsu1, Isao Takayanagi2, Junichi Nakamura1, Shou -Gwo Wuu3, Lyle Bainbridge4, Andrew Berkovich4, Song Chen4, Ramakrishna Chilukuri4, Wei Gao4, Tsung -Hsun Tsai4, Chiao Liu4
1Brillnics Japan Inc., Tokyo, Japan
2Brillnics JapanInc., Tokyo, Japan
3Brillnics Inc., Hsinchu, Taiwan
4Reality Labs, Meta Platforms Inc., Redmond, WA, USA

Abstract

We report improvement of a global shutter, stacked digital pixel sensor with 512 × 512, 4.6 μm pixels featuring an overlapped triple quantization scheme. It achieves an ultra-high dynamic range of 127 dB with reduced temporal noise and fixed pattern noise by pixel-design tuning and layout optimization. The new sensor chip achieves low power consumption of 5.8 mW, which is comparable to the original chip by design and operation optimizations despite the newly integrated voltage regulators for pixel power supply and pixel-control signals in the same die size as the original chip.
Publisher: IISS (Int. Image Sensors Society)
Year: 2023
Workshop: IISW
URL: https://doi.org/10.60928/oizm-zcg5
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Keywords

Global Shutter, Digital Pixel Sensor, Power Efficiency,

References

1) C. Liu, et al., "Intelligent Vision Systems – Bringing Human-Machine Interface to AR/VR", IEDM Tech. Dig., 2019. https://doi.org/10.1109/iedm19573.2019.8993566
2) C. Liu et al., "A 4.6 μm, 512×512, ultra-low power stacked digital pixel sensor with triple quantization and 127 dB dynamic range", IEDM Tech. Dig., Dec. 2020. https://doi.org/10.1109/iedm13553.2020.9371913
3) R. Ikeno et al., "A 4.6-μm, 127-dB Dynamic Range, Ultra-Low Power Stacked Digital Pixel Sensor With Overlapped Triple Quantization", IEEE Trans. Electron Devices, Jun. 2022. https://doi.org/10.1109/ted.2021.3121352
4) K. Mori et al., "A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range", IEEE Trans. Electron Devices, Jun. 2022. https://doi.org/10.1109/ted.2022.3164032
5) M. W. Seo et al., "A 2.6 e-rms low-random-noise, 116.2 mW low-power 2-Mp global shutter CMOS image sensor with pixel-level ADC and in-pixel memory", Proc. Symposium. VLSI Tech., Jun. 2021. https://doi.org/10.23919/vlsicircuits52068.2021.9492357
6) M. Sakakibara et al., "A 6.9-μm pixel-pitch back-illuminated global shutter CMOS image sensor with pixel-parallel 14-bit subthreshold ADC", IEEE J. Solid-State Circuits, Nov. 2018. https://doi.org/10.1109/jssc.2018.2863947
7) T. Takahashi et al., "A stacked CMOS image sensor with array-parallel ADC architecture", IEEE J. Solid-State Circuits, Apr. 2018. https://doi.org/10.1109/jssc.2017.2784759
8) H. Sugo et al., "A dead-time free global shutter CMOS image sensor with in-pixel LOFIC and ADC using pixel-wise connections", Proc. Symp. VLSI Circuits, Jun. 2016. https://doi.org/10.1109/vlsic.2016.7573544
9) C.-T. Ko, et al., "Wafer-level bonding/stacking technology for 3D integration", Microelectron. Rel., Apr. 2010. https://doi.org/10.1016/j.microrel.2009.09.015
10) P. Ramm, et al., "Handbook of Wafer Bonding", Hoboken, NJ, USA: Wiley, 2012. https://doi.org/10.1002/9783527644223
11) N. Akahane, et al., "Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor", IEEE Trans. Electron Devices, Nov. . 2009. https://doi.org/10.1109/ted.2009.2030550