WORKSHOP PAPER
Simple Technique to Reduce FPN in a linear-logarithm APS
Carlos A. de Moraes Cruz1,2, Davies W. de Lima Monteiro3, Gilles Sicard4, Alexandre K. P. Souza1
1Department of Electronics and Computation, Universidade Federal do Amazonas, Av. Gal. Rodrigo Octávio Jordão Ramos, 3000 - Coroado I 69077-000, Manaus, AM, Brazil
2Graduate Program in Electrical Engineering - Federal University of Minas Gerais, Av. Antônio Carlos 6627, 31270-901, Belo Horizonte, MG, Brazil
3Department of Electrical Engineering, DEE/PPGEE, Universidade Federal de Minas Gerais, Av. Antonio Carlos, 6627 - Pampulha 31270-010, Belo Horizonte, MG, Brazil
4TIMA Laboratory, CNRS, Grenoble INP, UJF, 46, avenue Felix Viallet, 38031 Grenoble, France

Abstract

This work presents a simple technique aimed at reducing fixed-pattern noise (FPN) in a modified 3T active-pixel-sensor (APS) operating in the linear-logarithmic mode. Through simulations, the proposed method demonstrated a capability to reduce total FPN by more than 80%, with the remaining FPN constituting less than 0.4% of the output signal swing in 120dB. The technique employs a double-sampling voltage reference scheme to suppress common offset FPN present in both samples, thereby offering an effective, straightforward solution to FPN reduction without increasing pixel or external circuitry complexity.
Publisher: IISS (Int. Image Sensors Society)
Year: 2013
Workshop: IISW
URL: https://doi.org/10.60928/ptkm-kra6

Keywords

Image Sensor, APS, FPN, Wide Dynamic Range,

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