WORKSHOP PAPER
Reconfigurable Focal-Plane Hardware for Block-Wise Intra-Frame HDR Imaging
Jorge Fernández-Berni1, Ricardo Carmona-Galán1, Ángel Rodríguez-Vázquez1
1Institute of Microelectronics of Seville (CSIC - Universidad de Sevilla), C/ Américo Vespucio s/n, 41092, Seville, Spain. Phone: +34954466666

Abstract

This paper presents circuitry conceived to be part of a massively parallel image processing array. Its main feature is a high degree of reconfigurability in order to extract different regions of interest (ROIs) across intra-frame high dynamic range (HDR) scenes. To this end, two photodiodes are included at each processing element (PE). One of them senses the pixel value whereas the other one, working collaboratively with the rest of PEs of the ROI, senses the average incident illumination on the region. As a result, the photointegration period for each ROI is asynchronously set during a single image acquisition stage. Another remarkable characteristic of the hardware is its low-power operation. We report some experimental results based on a previous prototype smart image sensor. By exploiting its processing capabilities, we emulate the behavior of the proposed circuitry. Direct applicability is demonstrated for the Viola-Jones vision algorithm.
Publisher: IISS (Int. Image Sensors Society)
Year: 2013
Workshop: IISW
URL: https://doi.org/10.60928/qju4-wk4u
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Keywords

HDR Imaging, Reconfigurable Hardware, Vision Algorithm,

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