WORKSHOP PAPER
A 400 × 400 3.24 μm 117 dB Dynamic Range 3-layer Stacked Digital Pixel Sensor with Triple Quantization and Fixed Pattern Noise Correction
Kwuang-Han Chang1, Tsung-Hsun Tsai1, Yi-Hsuan Lin1, Sheng-Yeh Lai1, Hao-Ming Hsu1, Hirofumi Abe2, Kazuya Mori2, Hideyuki Fukuhara2, Chih-Hao Lin1, Toshiyuki Isozaki2, Wei-Chen Li1, Wei-Fan Chou1, Chien-Chun Lee1, Wen-Han Tseng1, Wun-Young Leo1, Masayuki Uno2, Rimon Ikeno2, Masato Nagamatsu2, Guang Yang1, Shou-Gwo Wuu1, Andrew Berkovich3, Raffaele Capoccia3, Song Chen3, Zhao Wang3, Chiao Liu3, Lyle Bainbridge4
1Brillnics Taiwan Inc., Hsinchu, Taiwan
2Brillnics Japan Inc., Tokyo, Japan
3Meta, Redmond, WA, USA
4Sesame AI, San Francisco, CA, USA

Abstract

This paper presents a 400 × 400 digital pixel sensor (DPS) with the smallest 3.24 µm pixel size is developed in a 45nm/40nm/40nm three-layer stacked process. The sensor achieves a single-exposure 117 dB dynamic range (DR) incorporated with the overlapped triple quantization (3Q) and fixed pattern noise correction (FPN-C) while the noise floor of 4.4 e-rms and a dark FPN of 2.4 e-rms. This work consumes 3.06 mW at 30 fps with a FoM of 0.0049 e-rms × pJ and the die size of 2.47 × 1.85 mm2. This work is developed for high DR (HDR), low power consumption, and small form fact to meet the growing demands of augmented reality (AR) and virtual reality (VR) devices.
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/sm0g-j47e
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Keywords

Digital pixel sensor (DPS), in-pixel ADC, stacked process, 3D-IC, high dynamic range (HDR), triple quantization (3Q), fixed pattern noise (FPN), fixed pattern noise correction (FPN-C), lateral overflow integration capacitor (LOFIC), image signal processing (ISP), sparse transmission (ST), transmission map (TM), augmented reality (AR), virtual reality (VR),

References

[1]) T.-H. Tsai, "A 400×400 3.24μm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor", IEEE Int. Solid-State Circuits Conf. Dig., 2025. https://doi.org/10.1109/isscc49661.2025.10904717
[2]) C. Liu, "A 4.6 μm, 512×512, ultra-low power stacked digital pixel sensor with triple quantization and 127 dB dynamic range", IEEE Int. Electron Devices Meeting Dig, 2020. https://doi.org/10.1109/iedm13553.2020.9371913
[3]) R. Ikeno, "A 4.6-μm, 127-dB Dynamic Range, Ultra-Low Power Stacked Digital Pixel Sensor With Overlapped Triple Quantization", IEEE Trans. Electron Devices, 2022. https://doi.org/10.1109/ted.2021.3121352
[4]) K. Miyauchi, "A 3.96-μm, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple-and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation", IEEE J. Solid-State Circuits, 2022
[5]) P.-F. Rüedi, "A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems", IEEE Solid-State Circuits Letters, 2024. https://doi.org/10.1109/lssc.2024.3370797
[6]) M. W. Seo, "A 2.6 e-rms low-random-noise, 116.2 mW low-power 2-Mp global shutter CMOS image sensor with pixel-level ADC and in-pixel memory", IEEE Symp. VLSI Circuits Dig., 2021. https://doi.org/10.23919/vlsicircuits52068.2021.9492357
[7]) M. Sakakibara, "A 6.9-μm pixel-pitch back-illuminated global shutter CMOS image sensor with pixel-parallel 14-bit subthreshold ADC", IEEE J. Solid-State Circuits, 2018. https://doi.org/10.1109/jssc.2018.2863947
[8]) A. Berkovich, "A 3D-Integrated 2-Megapixel Imager with Sparse Capture and Fine-Grain Power Gating", IEEE Int. Electron Devices Meeting Dig., 2023. https://doi.org/10.1109/iedm45741.2023.10413713