WORKSHOP PAPER
A 40/22nm 200M P Stacked CMOS Image Sensor with 0.61µm Pixel
Abstract
We developed a new 40/22nm stacked 200 mega-pixel CMOS image sensor (CIS) with a 0.61 µm pixel. By using a 22nm logic wafer process node instead of 40nm , digital power consumption was reduced by half while keeping the same clock frequency, and the full high definition (FHD) frame rate was increased from 240fps to 480fps. In this work, we demonstrate a new source follower (SF) transistor architecture with 63% higher SF transconductance (Gm) compared with our former 0.7 µm pixel. A full well capacity (FWC) of 5.0ke- was achieved without lag or blooming, with better white pixel (WP) performance compared to the 0.7µm pixel. We demonstrate a 0.61µm quad photodiode (QPD) structure capable of achieving comparable quantum efficiency (QE) performance to 0.7 µm QPD in the visible light range.Keywords
CMOS Image Sensor, Pixel Technology, Quantum Efficiency,References
1) Yeongheup Jang et al., "A new PDAF correction method of CMOS image sensor with Nonacell and Super PD to improve image quality in binning mode", IS&T International Symposium on Electronic Imaging, 2021. https://doi.org/10.2352/issn.2470-1173.2021.9.iqsp-220
2) Albert Theuwissen, "There’s More to the Picture Than Meets the Eye*, and in the future it will only become more so", International Solid-State Circuits Conference (ISSCC), 2021. https://doi.org/10.1109/isscc42613.2021.9366058
3) Vincent C. Venezia et al., "Second Generation Small Pixel Technology Using Hybrid Bond Stacking", Sensors, 2018. https://doi.org/10.3390/s18020667
4) JongEun Park et al., "1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64µm Unit Pixels Separated by Full-Depth Deep-Trench Isolation", International Solid-State Circuits Conference (ISSCC), 2021. https://doi.org/10.1109/isscc42613.2021.9365751
5) Takuma Hasegawa et al., "A new 0.8µm CMOS image sensor with low RTS noise and high full well capacity", International Image Sensor Workshop, 2019. https://doi.org/10.60928/hsaw-fzn0
6) Y. Jay Jung et al., "A 64M CMOS Image Sensor using 0.7um pixel with high FWC and switchable conversion gain", IEEE International Electron Devices Meeting (IEDM), 2020. https://doi.org/10.1109/iedm13553.2020.9371889
7) Tetuya Okawa et al., "A 1/2inch 48M All PDAF CMOS Image Sensor Using 0.8µm Quad Bayer Coding 2x2OCL with 1.0lux Minimum AF Illuminance Level", IEEE International Electron Devices Meeting (IEDM), 2019. https://doi.org/10.1109/iedm19573.2019.8993499