WORKSHOP PAPER
0.64μm-pitch CMOS Image Sensor with Low Leakage Current of Vertical Transfer Gate
Abstract
This work discusses the challenges of reducing leakage current in CMOS Image Sensors (CIS) as pixel size decreases, particularly due to gate-induced drain leakage (GIDL) at the floating diffusion nodes (FD). The study introduces the integration of vertically etched Transfer Gates (VTGs) in a 0.64μm-pixel sensor, aiming for better charge transfer and reduced pixel area. Key findings include the identification of trap-assisted tunneling (TAT) as the primary GIDL mechanism and the optimization of VTG dry etch conditions and FD doping profiles to minimize chip-level variation of overlap capacitance (Cov), which in turn mitigates multi-bit white spot defects.Keywords
CMOS Image Sensor, Transfer Gate Transistor, Gate-induced Drain Leakage, Trap-assisted tunneling,References
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