WORKSHOP PAPER
Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage
J. Michelot1,2, F. Roy1, J. Prima1, C. Augier1, F. Barbier1, S. Ricq1, P. Boulenc1, Z. Essa1, L. Pinzelli1, H. Leininger1, M. Gatefait1, J.-E. Broquin2
1STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles Cedex – France
2Institut de microélectronique électromagnétisme et photonique – laboratoire d'hyperfréquences et de caractérisation (IMEP-LAHC), 3 Parvis Louis Néel – BP 257, F-38016 Grenoble Cedex – France

Abstract

A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pinned photodiode is investigated. The proof of a vertical pinning is made thanks to a study of the maximum diode depletion potential for different diode widths. Diode doping strategy is described in order to optimize in-depth charge storage. Simulation results show good matching when compared to scanning capacitance microscopy (SCM). A new silicon on insulator (SOI) wafer with embedded ONO broadband antireflective coating (ARC) fabrication technique is presented and demonstrates further improvement in terms of quantum efficiency (QE), with 63% in green spectrum. Process solutions such as additional thermal treatment are provided to control maximum diode depletion potential. A transfer gate (TG) is stacked above the photodiode and its according charge transfer technique is investigated. Pixel performances show full-well capacity of more than 11000 electrons.
Publisher: IISS (Int. Image Sensors Society)
Year: 2011
Workshop: IISW
URL: https://doi.org/10.60928/weee-efo6
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Keywords

Active pixel sensor, CMOS image sensor, backside illumination, full-well capacity, in depth charge storage, vertically pinned photodiode,

References

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