WORKSHOP PAPER
Piece-Wise-Linear Ramp ADC for CMOS Image Sensor and Calibration Techniques
C. Pastorelli1,2,3, P. Mellot1, S. Mir2,3, C. Tubert1
1STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France
2Université Grenoble Alpes, TIMA, 38000 Grenoble, France
3CNRS, TIMA, F-38000 Grenoble, France

Abstract

This paper proposes a 10-bit digital Correlated Double Sampling (CDS) high-speed CMOS Image Sensor designed in 65nm BSI technology for a 1.1µm pixel. The sensor's readout architecture, capable of processing a 13Mpix sensor (4248 x 3216) at 55 frames/s, is based on a Piece-Wise Linear (PWL) ramp generator implementing an I/C structure. The work investigates two innovative calibration techniques for output data linearization.
Publisher: IISS (Int. Image Sensors Society)
Year: 2015
Workshop: IISW
URL: https://doi.org/10.60928/xtsq-5y0l
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Keywords

CMOS image sensor, Piece-wise-linear ramp, Digital Correlated Double Sampling, Calibration,

References

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