WORKSHOP PAPER
Correlations between DCR and PDP of SPAD integrated in a 28 nm FD -SOI CMOS Technology
Abstract
This article presents an experimental study of the Dark Count Rate (DCR) and the Photon Detection Probability (PDP) of Single -Photon Avalanche Diodes (SPAD) implemented in 28nm Fully Depleted Silicon -On-Insulator (FD -SOI) CMOS technology. It proposes a TCAD simulation study correlating the experimental DCR and PDP results, showing a dependency of DCR and PDP with the amount of Shallow Trench Isolation (STI) oxide in the active zone and the alignment of the peripheral STI with the SPAD junction. Devices with more STI oxide tend to present higher DCR and PDP, with the experimental and TCAD simulation results both reflecting this trend.Keywords
SPAD, 28nm FD-SOI CMOS, Dark Count Rate DCR, Photon Detection Probability PDP, Shallow Trench Isolation STI, TCAD Simulation, Avalanche Triggering Probability ATP,References
1) M. Perenzoni et al., "A 160×120 Pixel Analog -Counting Singe -Photon Imager With Time -Gated and Self -Referenced Column -Parallel A/D Conversion for Fluorescence Lifetime Imaging", IEEE Journal of Solid -State Circuits, 2015. https://doi.org/10.1109/isscc.2015.7062995
2) I. Takai et al., "Single -Photon Avalanche Diode with Enhanced NIR -Sensitivity for Automotive LIDAR Systems", Sensors, 2016. https://doi.org/10.3390/s16040459
3) W. Jiang et al., "Time -Gated and Multi -Junction SPADs in Standard 65nm CMOS Technology", IEEE Sensors Journal, 2021. https://doi.org/10.1109/jsen.2021.3063319
4) S. Pellegrini et al., "Industrialised SPAD in 40nm technology", IEEE International Electron Devices Meeting (IEDM) 2017, 2017. https://doi.org/10.1109/iedm.2017.8268404
5) K. Morimoto et al., "3.2 Megapixel 3D -Stacked Charge Focusing SPAD for Low -Light Imaging and Depth Sensing", IEEE International Electron Devices Meeting (IEDM) 2021, 2021. https://doi.org/10.1109/iedm19574.2021.9720605
6) S. Shimada et al., "A Back Illuminated 6µm SPAD Pixel Array with High PDE and Time Jitter Performance", IEEE International Electron Devices Meeting (IEDM) 2021, 2021. https://doi.org/10.1109/iedm19574.2021.9720639
7) S. Shimada et al., "A SPAD Depth Sensor Robust Against Ambient Light: The Importance of Pixel Scaling and Demonstration of a 2.5µm Pixel with 21.8% PDE at 940nm", IEEE International Electron Devices Meeting (IEDM) 2022, 2022. https://doi.org/10.1109/iedm45625.2022.10019414
8) T. Chaves de Albuquerque et al., "Integration of SPAD in 28nm FDSOI CMOS technology", ESSDERC 2018, 2018. https://doi.org/10.1109/essderc.2018.8486852
9) D. Issartel et al., "Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR", Solid -State Electronics, Elsevier, 2022. https://doi.org/10.1016/j.sse.2022.108297
10) Z. You et al., "3µm Pitch, 1µm Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology", IISW 2017, 2017. https://doi.org/10.60928/uiwz-8hp2
11) A. Karz et al., "CMOS Single-Photon Avalanche Diode Pixel Design for a Gun Muzzle Flash Detection Camera", IEEE Transactions on Electron Devices, 2018. https://doi.org/10.1109/ted.2018.2866630
12) H. Ouh et al., "Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing", IEEE Journal of Solid -State Circuits, 2020. https://doi.org/10.1109/jssc.2019.2944856
13) M. Dolatpoor Lakeh et al., "An Ultrafast Active Quenching Active Reset Circuit with 50 % SPAD Afterpulsing Reduction in a 28 nm FD-SOI CMOS Technology Using Body Biasing Technique", MDPI Sensors, 2021. https://doi.org/10.3390/s21124014
14) S. Gao et al., "3D Electro-optical Simulations for Improving the Photon Detection Probability of SPAD Implemented in FD-SOI CMOS Technology", SISPAD conference, 27-29 Sept. 2021, 2021. https://doi.org/10.1109/sispad54002.2021.9592555