WORKSHOP PAPER
A 12-to-16-bit Column-Parallel CMS-based ADC for High Monotonically Linear Dynamic Range
De Xing Lioe1,2, Tomohiro Okuyama, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito
1SUiCTE Co. Ltd, 305 iPERC, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011, Japan
2Shizuoka University, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011, Japan

Abstract

This paper presents a 12-to16-bit column-parallel correlated multiple sampling (CMS)-based analog-to-digital converter (ADC), implemented in a 0.11 μm CMOS image sensor technology. The implemented image sensor has a resolution of 1080(H) x 1080(V) with a pixel pitch of 4.5 μm, and a die size of 9mm(H) x 10.44mm(V). The ADC features multiple per-cycle gains and 1.5b DAC per cycle. The measured peak temporal noise was reduced from 10.41 e-rms to 2.33 e-rms when varying the number of CMS from 4 to 64. By setting the analog gain to 4, the temporal noise was further reduced to 1.21 e-rms, at a conversion gain of 22.87 μV/e-. Additionally, the measured dark current distribution is 6.2 e-/s.
Year: 2025
Workshop: IISW
URL: https://doi.org/10.60928/zynh-nwy7
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Keywords

CMOS, sensor, column-parallel, ADC, cumulative, multiple, sampling, high, dynamic, range, folding, integration, cyclic,

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